VDC Research: Embedded Microprocessor, Board & Systems Market Blog

The End of Moore’s Law or Just the Beginning?

In 1965, Gordon E. Moore, the founder of Intel, noticed that the number of components in integrated circuits had doubled every year since their inception in 1958. Moore predicted that this doubling of components would continue at an annual rate for at least another 10 years. Nearly fifty years later, Moore’s Law, as it is commonly referred to today, continues to be the driving force behind the technological growth of the semiconductor industry. Despite its influence continually pushing innovations in processing speed, memory capacity, sensors, and even pixels in digital cameras, the general consensus amongst chip manufacturers is that Moore’s Law will soon come to an abrupt halt.

Rising costs of the manufacturing process have been linked most strongly with the demise of Moore’s Law. Chip designers’ ability to design such complex chips is falling behind the increasing demands of the manufacturing process. As a result, IBM estimated that Moore’s Law will come to an end sometime between 2015 and 2020. Robert Colwell, former chief architect for Intel, believes that the law could be dead, at the latest, by 2022. While it might be possible to build sub-5 nanometer chips by 2022, the expense and degree of duplication, so as to ensure proper functionality, will be far from cost-effective.

Chip manufacturers, including Intel, are well aware of the costly and complicated manufacturing techniques used in decreasing the size of embedded processors and realize that 5nm is likely the stopping point. Intel is currently working on implementing a 10nm chip by as soon as 2015. With the industry set for a new era of chip manufacturing past the 5nm benchmark, how exactly can Moore’s Law remain the industry standard? Well, plain and simple, Moore’s Law will end with transistors’ diminution. However, this does not mean to say that an entirely new law cannot be created; a law based on the premise of Gordon Moore’s original projection.

Quantum computers show the most promise for further development of integrated circuits. By combining quantum physics with semiconductor technology, we can potentially process information on a scale far beyond what is currently possible. Moreover, parallel computing can just as easily provide a platform for future economic growth and commercial innovation, as evidenced by the growing applicability of GPGPUs and similar technologies in embedded hardware. Carbon nanotubes have also burst onto the scene – outperforming silicon in terms of energy efficiency. We at VDC Research believe that the principal mechanics of Moore’s Law will continue to live on past the era of transistors and into burgeoning computing technologies like quantum computing, parallel computing, and carbon nanotubes.

by Conor Peal, Research Associate

For Microprocessor Vendors, The Enterprise Is Not the Future According to New Research from VDC Research

VDC is pleased to announce the publication of its annual outlook for the global market for embedded CPUs, MCUs and FPGAs.  This research is an invaluable strategic and tactical planning tool for chip, tool, and board vendors. 

Hightlights include:

• We expect ARM to continue to take CPU market share from Intel in the years to come, though Intel will succeed in defending its position in high-performance applications.

• Xilinx will cede FPGA market share to growing competitors Altera, Lattice Semiconductor, and Microsemi – who all stand to benefit from strong global demand for communications equipment, and OEMs’ continued migration away from ASICs.

• The MCU market will grow rapidly, with the automotive sector representing an increasingly large share of the market.

• Heterogeneous computing will drive big changes in the markets for all discrete processing technologies. As integrated architectures are used to consolidate functionality and boost processor efficiency, traditional vendors will need to deploy new business strategies to drive growth and margins.

• The importance of tools when selecting a chip will drive additional M&A activity, as large chip vendors swallow smaller tool providers.  Potentially attractive acquisition targets include DDC-I, IAR, or Lauterbach.

• The market for these embedded processing technologies (CPUs, MCUs and FPGAs combined) will grow to over $US 40 billion by 2017, at a compound annual growth rate of 6.9% overall.

To learn more download the executive brief now or see our recent press release here.

Embedded Processor Revenues (2012-2017)

The Great Divide: Growing Armies for High-end Server Applications

Several recent reports stemming from the keynote at least week’s JavaOne conference indicate that IBM is working towards enabling GPU acceleration with Java, one of the most popular programming languages used in software development. This shortly follows the establishment of the OpenPOWER Consortium, an open development alliance based on IBM’s Power architecture, in which an announcement was made that IBM and Nvidia will work together to integrate the Power and CUDA GPU ecosystems. At this point, its hard not to think about the competitive strategies unfolding of other industry leaders such as AMD, ARM, and Intel to capture the burgeoning server markets for high-performance computing (HPC) and big data applications. The end result will determine more than who carves out the most revenues, it will also decide the fate of several processor architectures and their extent in new enterprise applications.

First, from a software standpoint, IBM and Nvidia’s recent announcements will surely attract and retain a lot of developers. Not only is the collaboration enabling two pools of (typically deeply-invested) software developers to pursue more application opportunities, it will also add support for a common high-level language to which OEMs can easily acquire or build out expertise, Java. Nvidia is no newcomer to GPU acceleration in demanding big data applications, and teaming up with IBM to offer a more-holistic solution featuring more than its own proprietary CUDA language and GPU technology will improve integration with prospective businesses’ requirements and objectives.

On the other end, we have the splintering relationship between AMD and Intel. Traditionally an x86-only supplier, AMD will instead be also rolling out the first 64-bit ARM processors for datacenters in 2014, and will supply “processor-agnostic” SeaMicro servers and data center technology. Despite the sudden, uncomfortable ripples by AMD (whom will continue to supply x86 server chips as well), Intel’s x86 ecosystem is still widely used in datacenters around the world. Furthermore, the company has its own line of computing products to compete with GPU acceleration – the Xeon Phi coprocessors, launched in mid-2012. Intel’s processors and coprocessors use common languages, models, and tools – maximizing developer support and preserving software expertise across the Xeon product line.

IBM and Nvidia’s growing relationship is hugely important for each company. Neither on its own would likely make a significant impact in the markets for large and hyperscale computing with respect to Intel and ARM’s growing influence. However, bridging popular CPU and GPU architectures will bode well for CUDA and Power as OEMs increasingly employ heterogeneous architectures to realize the flexibility in simultaneous processing of serial and parallel workloads. 

Sometimes Less Can Be More - A Lot More!

As you may recall, AMD won VDC’s Hardware Embeddy for the new G-Series SoC processors. The G-Series line of these processors continues to expand and this week provides another example of the broadening of that line to address lower TDP applications .

With a maximum Thermal Design Power (TDP) of only 6 Watts the GX-210JA SoC formally announced this morning consumes a third less power than what was, until today, the lowest power G-Series member. On average, and depending on the application, AMD projects the new product will exhibit 3 Watts TDP. This may not seem like a big deal but it is if you are an OEM looking to rollout a new product where the available budget for power and cooling are low but, at the same time, the applications running on the product required dual-core processing and graphics capability. The new GX-210JA features a dual-core running at 1 GHz and a GPU core running at 225MHz.

How did AMD make this breakthrough while still using a 28nm process? There were actually a couple of simple steps. First of all, they turned off support for VGA as the analog driver components were guilty of consuming more power than the benefits they supply to the few, if any OEMs that still use VGA. On a similar note, USB 3.0 was also not supported with the theory that USB 2.0 was sufficient for most applications. It is also possible that AMD uses a few process tweaks and some form of selectivity to produce the GX-210JA.

Where could this new AMD product find market traction? We certainly have a few ideas. First of all, we believe that Video Surveillance as a Service (VSaaS) will be a significantly growing market for embedded computing suppliers. VSaaS will need thin-clients with graphics processing co-located at camera installations to perform the video transcoding needed for transmission to cloud resources. In some places where surveillance cameras are placed, the available power and environment will not favor products that require fans. A 6 Watt TDP embedded processor can easily be used in fanless computers without the OEM needing to use extravagant heat sinks.

In summary, the GPU on the G-Series can be used for that VSaaS application just as easily as it could be for supporting HMIs and displays. This brings us to signage, gaming, and medical devices where informative and intuitive displays can differentiate an OEM’s product.  The 225Mhz GPU may not have the performance for 3D or other challenging video applications but, that is not an issue for many of the product types we mentioned. Less is sometimes a lot more.

Graphics Titans Share the Cache and Heterogeneous Architectures Gain from It

Heterogeneous computing is picking up steam with the latest announcements surrounding AMD’s Kaveri chipset and NVIDIA’s Maxwell GPU. Both chips will employ unified memory technologies in which the CPU and GPU can access main memory in tandem. The vast benefits of bridging different processing technologies closer together is why both of these graphics titans continue increasing support and unveiling products featuring heterogeneous architectures. This is why heterogeneous computing will continue to gain traction in several applications, and why embedded end users should prepare for support now.

AMD has done much preparing for Kaveri, featuring the company’s second generation Heterogeneous System Architecture (HSA) which includes the aforementioned Heterogeneous Uniform Memory Access (hUMA). AMD’s hUMA allows for easier sharing of resources within the upcoming Kaveri APU, with features such as Coherent Memory and Pageable Memory. The company leads the HSA Foundation, a non-profit consortium of various semiconductor players with the common goal of simplifying heterogeneous programming – the leading barrier to adoption. The foundation released its first specification in May 2013 and continues to garner contributors and support.

Unified Virtual Memory, NVIDIA’s memory enhancement to the Maxwell GPU, will also allow for shared DDR main memory to enable better memory handling and increased memory bandwidth. The Maxwell GPU will be NVIDIA’s first architecture able to access main memory. NVIDIA’s CUDA parallel computing platform enhances the programmability of heterogeneous platforms, with support for popular languages such as C, C++, C#, Fortran, Java, Python, and more.

Heterogeneous computing enables vast benefits for applications such as console gaming, high-performance computing, life sciences, and more. These upcoming technologies will force end users and developers to adapt to new programming models and interfaces. However, AMD and NVIDIA realize their end markets will only buy what they are capable of using and will continually push support for their respective programming platforms – which is inevitably pushing us towards a heterogeneous future.

OEMs Shift Their Use of Professional Services to a Gain Competitive Edge

In 2013, VDC is seeing dynamic shifts in strategy for many OEMs as they respond to market pressures and position their organizations for future opportunities. As the economy improves, the calculus behind the professional services decision may change but most OEMs still prefer to outsource non-core functions. Although the OEM may be losing some product margin to pay for the services consumed, it is a small price to pay compared to the expense and risk of bringing processes back in house. Even so, we see that 10% of OEMs will be considering re-joining the 20% of their peers that do not utilize any professional services (Exhibit 1).

Exhibit 1: 2013 OEM cited current and future use of professional services

In these cases where the reduction in professional service use is being considered by the OEMs, there could be multiple forces and strategies at work. Sometimes it can be as simple as the OEM’s belief that if they want to do something right, they have to do it themselves. It also can be the result that recapturing the lost margins is worth the organizational costs and risks given the improving unit volumes. Although improving margins through insourcing may be part of the strategy, the largest gains are obtained when an OEM can better differentiate their product and therefore charge a premium price for it. Therefore, it is likely that OEMs with proprietary processes and technologies that provide differentiation feel they need to insource to protect their intellectual property.

Despite the advantages that insourcing may have, a growing majority of OEMs see outsourcing as the best way for reducing development costs while still being able to take advantage of new technologies. A prime example might be the new 4^th generation of i7 processors being rolled out by Intel. If an OEM was going to directly embed them, they would need to gain expertise and knowledge of the new Z87 Express chipset. It also might be difficult for an OEM to even obtain those components because they are likely to be in tight supply and the Intel alliance partners would be in a position to have better access. For similar reasons, an OEM would be better off looking to an embedded supplier for an AMD G-Series SoC based hardware product. In that case, the OEM could be focusing their internal resources on activities to develop an HMI application that fully utilized the embedded graphics capability. Doing so could make their product sparkle in ways a competitor might find difficult to duplicate let alone surpass.

At the Design West – Embedded Systems Conference 2013 – Part 1 the Embeddy

Last week, while attending the 2013 DESIGN West/Embedded Systems Conference in San Jose we presented the VDC Research Embeddy Award for the best new embedded hardware product. As part of the selection process the VDC Embedded Hardware team met with more than 30 companies to discuss product announcements and a variety of industry trends impacting the embedded hardware market today. Before we get to the award winner, we will start with a few highlights from some of the suppliers we spoke to at the show.

Connectivity enhanced Microcontrollers: Microchip usually makes several significant embedded hardware announcements at DW/ESC shows and this year was no exception.  VDC was given a detailed briefing on several new connectivity modules that OEMs can use for many applications. If the OEM's product already has a computing element, the new microchip modules are designed to easily integrate the needed Bluetooth, Wi-Fi, ZigBee, MiWi, and/or proprietary network types. If the OEM’s engineers have not settled on a processing element to interface with sensors or product components they might consider the modules that include integrated MCUs. The good news for OEMs is that the selection of any of these Microchip modules will likely eliminate product testing for overall FCC compliance and production test and calibration. Microchip demonstrated how a lighting OEM might integrate these new products in a way that would enable lighting products to be controlled in M2M applications including network based portals and authenticated mobile devices.

Secure M2M: Our next stop at the show was with Icon Labs and they were highlighting a new barrier/firewall device that was well suited for supporting M2M on legacy equipment in industrial applications. The unit we saw was targeted for a market price of ~$1K but included many security elements using Intel Atom processing and embedded software from Icon Labs’ partners including Wind River, ZiLog, McAfee, and Green Hills.

New Rugged Handheld Devices: At our next stop, the VDC EHW team was greeted by the enthusiastic ADLINK team and they had every right to be that way. There were a number of interesting products in many categories.  We were particularly interested in ADLINK’s foray into the enterprise handheld device market with the IMX-9000 which includes barcode reading capability, multiple connectivity protocols all contained in a stylish but rugged enclosure that is said to withstand IP67 and 1.5M drop tests. While at the ADLINK booth, we saw the new Advanced TCA processor blade. The new aTCA-9300 is well suited for media delivery platforms because of the need for scalable processing to deliver content in the needed forms and formats for the transmission and end use by the target device.

Media Processing: As a bit of background, it is not feasible to store content in all forms and formats suitable for delivery to, and use by, the huge numbers of things used to view them. This means that content has to be converted on the fly and that means there is a huge need for embedded processing products to perform these tasks.

ASICs and FPGAs: We received updates on the latest developments in the world of ASICs and FPGAs. We spoke with Altera who divides the majority of the FPGA market with Xilinx.  Altera  provided an update on the SoC FPGA line that was introduced in late 2011. The Cyclone V and Arria V FPGAs incorporate ARM CPU cores with FPGAs to allow OEMs to develop more powerful and flexible product designs while economizing on needed circuit board space.  One advantage that FPGAs normally have over ASICS is that they take less time to design and can be brought into production faster. If design issues are discovered at later stages, they can be corrected faster and at lower cost. The Altera inclusion of ARM cores allows OEM engineers to leverage many development tools that are available for ARM and that theoretically increases the advantages over traditional ASIC processes.

On the ASIC side, we received a briefing by Triad Semiconductor on their ViaASICs  and the associated development toolset ViaDesigner. The goals of these two products is to eliminate the time-to-market and development cost advantages of FPGA products over ASICs. The process works like this. In the semiconductor fab, the wafers are started and arrays of circuits and functional blocks are laid down but not configured and interconnected. These are then stocked until needed. An OEM engineer then uses the development tool that determines how the Triad chip will be configured. The data from that tool is sent to the fab and they create the mask(s) needed to for the next steps in the wafer creation process. The next steps lay down the layers needed for connecting the functional blocks creating a finished product.

New SBCs: Advantech highlighted a new compact design Single Board Computer (SBC) called the MIO-5290 that can be ordered with 3^rd Gen Intel i3 or i7 processors. With its ability to drive 3 independent displays with intense graphics, and the availability to add various I/O modules to customize the product, the MIO-5290 is well suited for many applications such as intelligent signage. The VDC team identified the MIO as one of the finalists in the Embeddy Award selection process.

Another finalist in the Embeddy Award selection process was WinSystems SBC35C series of products that utilize the 800 Mhz Freescale  i.MX 6Q Industrial Processor. There were several things that impressed us. The SBC35C board layout was very well thought out with industrial bus connections all on one side and the other needed connections on the other. The SBC35C can be run with Power over Ethernet (PoE) or a single DC source. The last thing that impressed us was the fact that the WinSystems team was showing their product the proper respect by handling the demo SBC with an anti-static bag. If they do that on the show floor, you can expect that their production and test process is also using similar precautions.

2013 Hardware Embeddy Winner: And now, without further ado, the winner of the VDC Hardware Embeddy award for the 2013 Design West / ESC show was AMD for their new G-Series family of SoC processors that we believe will make a big impact in the embedded hardware market.

ALPR = Big $$ for Embedded Hardware Suppliers

An interesting opportunity for embedded hardware suppliers caught the attention of the VDC M2M Embedded Platform team. The opportunity was highlighted in a Boston Globe article this week about a local police department that equipped a cruiser with a $28K Automatic License Plate Reader (ALPR) unit. There were a number of eye-popping statistics starting with the fact that the unit apparently paid for itself in the first 11 days it was deployed. The ROI was accomplished from revenues generated by identifying vehicles and drivers with expired licenses, registrations, inspections, or other unpaid fines and fees. ALPRs can also be used for parking enforcement particularly in areas where civilian officials want to encourage shoppers with low cost short interval parking spaces. In this parking application, an official uses an ALPR to detect commuters and/or store workers that try to take advantage of the potential arbitrage and fine them.

Now let’s look at the $28K bundle of embedded hardware and software and speculate a bit on what is likely to be involved. The ALPR cited by the Boston Globe had the capability to read 1,800 license plates per minute and cover 4 lanes of traffic simultaneously. It can make those readings at differential speeds of up to 150 mph. This is a key factor because the unit is mounted on a cruiser as opposed to a parking or toll-taking lane where only the vehicle would be moving and the zone where the license plate would be is more predictable. Therefore there has to be a camera system capable of capturing a wide field at varying focal lengths and light conditions. The torrent of data from the camera system has to be rapidly processed to identify license plates and simultaneously perform Optical Character Recognition (OCR) on 4 or more plates in the field of view. Additionally, the system has to identify the state that issued the plate. This is challenging because many states like Massachusetts issue multiple types of specialty plates for sports teams and other organizations or causes. States also control costs by not replacing license plates until they practically fall apart. Therefore, it is fairly safe to say that there would be approximately $10K in optics and high performance processing inside the ALPR to accomplish the OCR function.

What happens next is important. We are going to make an assumption and it is a big one. We will assume that the ALPR generates data that supports law enforcement but this data will not be a cornerstone for court cases. This means that the raw video would not need to be compressed and stored for future reference while preserving chain of custody. For example, if the ALPR were going to be used for moving traffic or criminal violations it would need to have irrefutable video evidence that identified the driver as well as speed measurement data. Because of our limited OCR assumption, the captured data only needs to be combined with time stamps, GPS coordinates and, perhaps a few operational parameters. As a result, this limited data set would be in the order of kbytes per record as opposed to Mbytes per second for full video archiving. Even so, this still represents several thousands of dollars per ALPR unit for the additional embedded sensing, processing, storage, HMI and communication hardware.

In our estimate, the next part of the ALPR application would optimally involve cloud-based Big Data resources. The ALPR would transmit captured data in real time and processed for matches in multiple databases. The response back to the police cruiser would have to be rapid to be effective. The most effective ALPR supporting infrastructure would have to combine data from all municipalities, states, and federal agencies relevant to a particular region. Suffice it to say, the cloud-based and communication services could easily amount to several hundred dollars per month for each ALPR deployed.

The Boston Globe article stated that there were already 87 ALPRs deployed in the state with another 7 Boston area police departments adding 21 additional in the next month. Considering that Massachusetts alone has over 350 cities and towns but the entire US represents over 36,000 municipalities, the potential market for ALPRs and the embedded hardware inside them would appear to be a huge and rapidly growing opportunity.

Moore’s Law – Where Do We Go From Here? (Part 3)

Of Carbon Nanotubes and Small Groups of Atoms

In the first two installments of this blog series (Part 1)(Part 2), we’ve touched on a variety of new developments that may allow continuing miniaturization, despite predictions of doom from some pundits. We’ve talked about some interesting things like single atom transistors, 3-D ICs and extreme ultra-violet lithography.  Although conventional wisdom places the limit of silicon transistors at about 11 nm, some folks at Intel have said that they have a solution for shrinking silicon down to 10 nm, and think that they may be able to go as far as 5 nm. But the science-fiction nut in me is most fascinated by new developments at IBM and Berkeley.

Terrestrial life as we know it is, of course, based on carbon. SF writers – and, indeed, some scientists – have proposed that, because carbon and silicon share many chemical properties (for example, the ability to form long-chain polymers), it might be possible to not only derive a silicon-based organic chemistry, but to actually have silicon-based life somewhere in this wondrous and infinite universe. Interesting, but as yet still science fiction.

However, what if we were to turn this around, and look at carbon and silicon from another angle? That’s essentially what’s going on at IBM, Berkeley and other research facilities.

As we all know, today’s semiconductor technology is based on silicon. But what if we were to substitute carbon for silicon? Would it be possible to create carbon-based semiconductors? Carbon atoms are far smaller than their silicon counterparts, so this might enable heretofore unimaginable miniaturization.

IBM’s people have successfully fabricated and evaluated a structure comprising an array of 10,000 carbon nanotube transistors on a single substrate. In essence, a carbon nanotube is a single-atom thick sheet of carbon, rolled into a tube. Normally, these appear as a mix of metallic and semiconducting types but, to create a computing device, the metallic types must be removed. And, as if that wasn’t tough enough, the placement and alignment of the tubes on a substrate must be precisely controlled. IBM has been able to accomplish this utilizing ion-exchange chemistry. Researchers at Berkeley have been able accomplish a similar feat, producing arrays both flexible and stretchable, which show great promise for developments such as foldable electronic pads, coatings that can monitor surfaces for cracks and other potential failures, “smart” clothing and even artificial electronic skin.

It is theorized that carbon nanotube transistor arrays, which can be produced with existing manufacturing processes, have the potential to yield CPU structures that are not only far smaller than their silicon counterparts, but are five to ten times faster than today’s silicon chips.

It’s not clear to me whether a single nanotube can only carry a single transistor, or whether it might be possible to produce many transistors at different locations on the surface of a single nanotube. While the latter may not be “do-able” today, who can say what will be possible tomorrow?

IBM scientists have also been able to determine that only twelve atoms are required to magnetically store a single bit of information. This is accomplished by precisely aligning their magnetic properties such that they do not interfere with other groups of atoms located nearby. It is projected that this technology could increase magnetic storage density on a hard disk drive by a factor of 100.

I suppose (though this is pure speculation) that it may also be possible to create ultra-dense storage through the use of carbon nanotubes. And, since nanotubes are inherently 3-D structures, they may lend themselves to the fabrication of 3-D chips as well.

Whatever happens, two things are clear to me. First, we are nowhere near the end of miniaturization and, second, the ability to produce computing devices with human, or even superhuman, computing ability may be fairly close. Can the development of truly intelligent machines with the ability to both replicate and evolve be that far away? I certainly hope I’m still around to see this.

The Next big Thing in Smart Phones is LITTLE

Last week, Samsung unveiled its latest Galaxy S4 Smartphone. The first wave of news indicated that it would be powered by Samsung’s new 8-core Exynos 5 octa processor.  This is exciting to us because it represents one of the first commercial rollouts of the ARM big.LITTLE technology.  Samsung intends to sell the Exynos 5 to other device makers as well. These types of processors although targeted for use in high-end mobile devices, may find M2M and embedded market traction as well because of the many functions that are included and the technology that balances processor speed and power consumption.

The Exynos 5 octa includes four powerful A-15 cores, each one paired with a subsidiary “energy sipping” A-7 core. The ARM technology allows seamless switching from one core to the other, depending upon the application. This heterogeneous approach allows the Exynos 5 to be as much as 70% more efficient than processors utilizing homogeneous cores.

The use of heterogeneous cores is not new, but other versions we have seen often have required some application design finesse to achieve a balance between energy conservation and performance. ARM’s big.LITTLE architecture, on the other hand, allows software developers to concentrate on the use of the four A-15 cores because the instruction sets for the A-15s and the subsidiary A-7s are the same.

Smartphones are not the only mobile products that can benefit from the big.LITTLE technology and processors such as the Exynos 5 octa. If Samsung or another supplier commit to making these military and/or industrial versions of these devices and to making them available for the extended periods of time that these markets require, we might see them make inroads in areas such as telematics M2M and/or micro unmanned platforms. These small-sized platforms have to operate autonomously for as long as possible, so power available for processing is a precious commodity. As with smartphones, loads on processing in mini unmanned and M2M platform applications can vary significantly, depending on the situation. Therefore, a 70% energy efficiency improvement might become the difference between a successful mission and one that is terminated before reaching its goal.

As this blog is posting, there is some information to suggest that the North American release of the Samsung S4 may not use the Exynos, instead using the Qualcomm Snapdragon 600. There are a few possible reasons for this potential processor swap. The first being given is that US carriers are presently more receptive to Qualcomm’s cellular modem technology. We believe that it is also possible that the supply of Exynos 5 octa chips is limited because of wafer fab capacity or yields. Lastly Samsung, like many phone suppliers, keeps each product platform fresh by introducing new derivatives. These incremental upgrades can serve to keep products popular with consumers, thereby maintaining revenue margins for suppliers and cellular providers.